1. Field
Exemplary embodiments of the present invention relate to a resistive memory device, and more particularly, to a resistive memory device with operating stability.
2. Description of the Related Art
Generally, a fuse may be programmed in the wafer stage of a semiconductor device because data are sorted out depending on whether the fuse is cut by a laser or not. After the wafer stage of the semiconductor device is mounted as the package stage of a chip, the fuse may not be programmed.
An e-fuse, however, is used to be programmed in the various stages of the device. An e-fuse stores a data by using a transistor and changing resistance between a gate and a drain/source to the transistor.
FIG. 1 illustrates an e-fuse formed of a transistor and operating as a resistor or a capacitor.
Referring to FIG. 1, the e-fuse is formed of a transistor T, and a power supply voltage is applied to a gate G of the transistor T while a ground voltage is applied to a drain/source D/S thereof.
When a power supply voltage having such a voltage level that the transistor T may bear is applied to the gate G, the e-fuse operates as a capacitor C. Therefore, no current flows between the gate G and the drain/source D/S. When a high power supply voltage having such a voltage level that the transistor T may not bear is applied to the gate G, a gate oxide of the transistor T is destroyed to cause the coupling between the gate G and the drain/source D/S and the e-fuse operates as a resistor R. Therefore, current flows between the gate G and the drain/source D/S. According to this phenomenon, a data of an e-fuse is recognized based on the resistance value between the gate G and the drain/source D/S of the e-fuse. Here, the data of the e-fuse may be stably recognized by 1) enlarging the size of the transistor T or by 2) using an amplifier and amplifying the current flowing through the transistor T instead of increasing the size of the transistor T. The two methods, however, have a dimensional restriction because the large size of the transistor T is to be designed or an amplifier for amplifying a data is to be added to each e-fuse.
U.S. Pat. No. 7,269,047 discloses a method for decreasing the area occupied by an e-fuse by forming an e-fuse array.
FIG. 2 is a circuit diagram of a conventional cell array 200 including e-fuses.
Referring to FIG. 2, the cell array 200 includes memory cells 201 to 216 that are arrayed in N rows and M columns. The memory cells 201 to 216 include memory elements M1 to M16 and switch elements S1 to S16, respectively. The memory elements M1 to M16 are e-fuses having characteristics of a resistor or a capacitor depending on whether fuse-rupturing has occurred or not. In other words, the e-fuses M1 to M16 may be regarded as a resistive memory device for storing data depending on the value of its resistance. The switch elements S1 to S16 electrically connect the memory elements M1 to M16 with column lines BL1 to BLM under the control of row lines WLR1 to WLRN.
Hereinafter, it is described that a second row is a selected row and an Mth column is a selected column. In other words, it is described that a memory cell 208 is a selected memory cell. Hereinafter, voltages applied to the selected memory cell 208 and unselected memory cells 201 to 207 and 209 to 216 during a program/read operation are described.
Program Operation
The row line WLR2 of the selected row is enabled and the other row lines WLR1 and WLR3 to WLRN are disabled. As a result, switch elements S5 to S8 are turned on, and the switch elements S1 to S4 and S9 to S16 are turned off. While a high voltage, which is generally generated by pumping a power supply voltage, is applied to a program/read line WLP2 of the selected row so as to destroy a gate oxide of an e-fuse, and a low-level voltage such as a ground voltage is applied to the other program/read lines WLP1 and WLP3 to WLPN. The selected column line BLM is coupled with a data access circuit, and the unselected column lines BL1 to BLM-1 are floated. The data access circuit supplies the selected column line BLM with a low-level voltage and programs a memory element M8 of the selected memory cell 208, when an inputted data is a program data, e.g., ‘1’. The gate oxide of the memory element M8 may be ruptured by being programmed. When an inputted data is not a program data, for example, when the inputted data is ‘0’, the data access circuit supplies the selected column line BLM with a high-level voltage and does not program the memory element M8 of the selected memory cell 208. Since the unselected column lines BL1 to BLM-1 are floated, the memory elements M5 to M7 are not programmed although a high voltage is applied to the gates thereof.
Read Operation
The row line WLR2 of the selected row is enabled and the other row lines WLR1 and WLR3 to WLRN are disabled. As a result, switch elements S5 to S8 are turned on, and the switch elements S1 to S4 and S9 to S16 are turned off. An appropriate level of voltage for a read operation, which is generally a power supply voltage, is applied to a program/read line WLP2 of the selected row, and a low-level voltage such as a ground voltage is applied to the other program/read lines WLP1 and WLP3˜WLPN. The selected column line BLM is coupled with a data access circuit, and the unselected column lines BL1 to BLM-1 are floated. The data access circuit recognizes that the memory element M8 is programmed when current flows through the selected column line BLM. In short, the data access circuit recognizes the data of the selected memory cell 208 as ‘1’. When no current flows through the selected column line BLM, the data access circuit recognizes that the memory element M8 is not programmed. In short, the data access circuit recognizes the data of the selected memory cell 208 as ‘0’.
It is illustrated above that one column line BLM is selected among the multiple column lines BL1 to BLM, but a plurality of column lines may be selected at one time. In short, a plurality of memory cells belonging to one row may be programmed/read simultaneously.
FIG. 3 is a block diagram illustrating a conventional resistive memory device including the cell array 200 shown in FIG. 2.
Referring to FIG. 3, the resistive memory device includes the cell array 200, a row circuit 310, a column decoder 320, and a data access circuit 330.
The row circuit 310 controls row lines WLR1 to WLRN and program/read lines WLP1 to WLPN to perform the program and read operations described above. An address ROW_ADD inputted to the row circuit 310 designates a row that is selected among a plurality of rows, and a program/read signal PGM/RD commands the memory device to perform a program operation or a read operation.
The column decoder 320 electrically connects a column line selected based on an address COL_ADD among a plurality of column lines BL1 to BLM with the data access circuit 330. The drawing illustrates a case that 8 column lines are selected among the column lines BL1 to BLM.
The data access circuit 330 is in charge of data access with the column lines selected by the column decoder 320. During a program operation, the data access circuit 330 controls the selected column lines to be programmed or not based on input data DATA<0> to DATA<7>. During a read operation, the data access circuit 330 senses whether current flows through the selected column lines and outputs a sensing result as an output data DATA<0> to DATA<7>.
The resistive memory device stores data by destroying or not destroying a gate oxide of a transistor that forms an e-fuse. Destroying the gate oxide may depend on the characteristics of the transistor. In other words, an error may occur in programming the resistive memory device depending on the characteristics of the transistor. Meanwhile, the resistive memory device is used to store a data that may be maintained permanently in a system, such as a repair data in a memory device, i.e., a Dynamic Random Access Memory (DRAM) device and a flash memory device. Reliability is significant for these kinds of data. Therefore, a resistive memory device is being developed to increase the data reliability thereof.